Tech Summit
Charles JanacArterisArteris

Charles Janac

Chairman, President & CEO

Mr. Janac is president and CEO of Arteris IP where he is responsible for growing and establishing a strong global presence for the company that is pioneering the concept of NoC technology. Charlie’s career spans 20 years and multiple industries including electronic design automation, semiconductor capital equipment, nano-technology, industrial polymers and venture capital.

In the first decade of his career, he held various marketing and sales positions at Cadence Design Systems (NASDAQ: CDNS) where he helped build it into one of the ten largest software companies in the world. He joined HLD Systems as president, shifting the company’s focus from consulting services to IC floor planning software and building the management, distribution and customer support organizations. He then formed Smart Machines, manufacturer of semiconductor automation equipment and sold it to Brooks Automation (NASDAQ: BRKS). After a year as Entrepreneur-in-Residence at Infinity Capital, a leading early-stage Venture Capital firm, where he consulted on Information Technology investment opportunities, he joined Nanomix as president and CEO helping build this start-up nano-technology company.

Mr. Janac holds a B.S. and M.S. degree in Organic Chemistry from Tufts University and an M.B.A from Stanford Graduate School of Business.



Arteris is a leading provider of interconnect and other intellectual property (“IP”) technology that manages the on-chip communications in System-on-Chip (“SoC”) semiconductor devices. Our products enable our customers to deliver increasingly complex SoCs that not only process data but are also able to make decisions. Growth in the total addressable market for our solutions is being driven by fast-growing market segments such as artificial intelligence & machine learning (AI/ML), autonomous driving & electric vehicles, and the buildout of 5G wireless infrastructure. These markets demand highly complex chips consisting of more processors, machine learning accelerators, memory access channels, chiplets, input/output interfaces and other subsystems. The growth in the complexity and numbers of these connected on-chip subsystems places an increasing premium on the on-chip interconnect IP’s capability to optimize data flow within these SoCs and drives adoption of our IP deployment technology to accelerate the SoC development process.